The technical field generally to integrated circuit design. More particularly, the technical field relates to a method for adding de-race buffers to maintain signal integrity in a circuit design having state elements and combinatorial elements.
An electronic circuit design may comprise both state elements, such as latches, and combinatorial elements, such as logic gates. As used herein, state elements include those elements capable of storing date over multiple clock cycles. In a state element, a change on an input results in a change at the output, if any, upon the receipt of a clock signal. Combinatorial elements refer to all other circuit elements that process input signals as they are received, rather than waiting for a clock signal. A design, or a portion of a design, may include both state elements and combinatorial elements interconnected, such that an output of a state element is connected to an input of a combinatorial element, and vice versa. A single clock signal may control multiple state elements in a design.
A timing problem occurs when a signal does not propagate through the circuit within specifications of the clock. A signal may have a maximum allotted time to pass from a source, such as an upstream state element, to a receiver, such as another state element located xe2x80x9cdownstream.xe2x80x9d As used herein, that maximum time is referred to as the xe2x80x9cmax-time.xe2x80x9d For example, a design may specify that a signal reaches a certain point in the circuit, such as the next state element, during a single clock cycle or a number of clock cycles. If the signal does not reach the specified point in the circuit within the max-time, a timing problem results and the circuit design does not meet the design""s frequency goals. A signal may also have a minimum time allotted to pass from a source to a state element. Even though state elements may use the same clock input, the clock may be received at one state element later than it is received at another state element, for example due to clock skew. If a signal reaches a state element before the clock cycle, it may xe2x80x9cracexe2x80x9d through the state element, producing an incorrect output. The minimum time, referred to as the xe2x80x9cmin-time,xe2x80x9d ensures that the signal does not reach the state elements before the appropriate clock cycle.
One way to ensure that the design meets the min-time specifications is to delay the signal by adding de-racing buffers, also referred to as xe2x80x9cde-racers.xe2x80x9d As used herein, de-racer refers to any element that delays a signal. Existing methods and systems require designers to place de-racers manually or as part of a complicated synthesis flow. This is a difficult task because a path from a source to a state clement may have multiple signals entering and exiting. In some instances, it may be desirable to have a minimum number of de-racers in the circuit, so the de-racers may be positioned directly in front of recipient state elements. However, this implementation affects all paths to that state clement when only some of the paths may have min-time problems. Moreover, addition of a de-racer may cause some paths to break their max-time specifications. A designer must ensure that the de-racer not only solves the min-time violation, but also keeps the design within max-time and other specifications. Addition of a de-racer may potentially cause max-time problems for other signals. In a complex circuit, this process generally requires the designer to analyze multiple signals along a path between state elements through a process of trial and error. What is needed is a more efficient method and system for resolving min-time violations.
What is disclosed is a method for testing an integrated circuit design to resolve min-time violations, including analyzing a first state element to identify a min-time violation, determining if adding a de-racer to an input gate of the first state element creates a critical path, and if a critical path is not created, adding the de-racer. If a critical path is created, the method includes backtracking to an upstream element, and determining if adding the de-racer to a first input gate of the upstream element creates a critical path.
Also disclosed is a method for resolving min-time violations in an integrated circuit design, including analyzing a first path to a first element in the circuit to identify a min-time violation, determining if the first element is a new state element if the first element is not a new state element, determining if a new global output is to be de-raced; and if the new global output is to be de-raced, backtracking through the circuit to an upstream state element.
Still further what is disclosed is a method for resolving min-time violations in an integrated circuit the method includes the steps of identifying a first element having a min-time violation, and determining if the first element can be de-raced. The step of determining if the first element can be de-raced includes determining if the first element includes a latch, if the first element includes a latch, determining if adding a de-racer creates another timing violation, if adding the de-racer creates another timing violation, returning a cannot de-race response, and if adding the de-racer does not create another timing violation, adding the de-racer.